In the manufacture of vertical bipolar transistors in a BiCMOS integrated circuit, Typically, the emitter of the bi-polar device is formed after certain CMOS type devices have been created. Accordingly, the one or more layers with which the emitter are formed overlay the prior created CMOS devices, such as, for example, a gate stack formed over a drain and source region. Exemplary descriptions of the various processes for forming a BiCMOS device and the various steps in its manufacture are disclosed in U.S. Pat. Nos. 6,359,317; 6,797,580 and 5,422,290 which are incorporated herein by reference. A typical manufacturing sequence involves the deposition of an oxide layer, followed by depositing a polysilicon layer, then a hard mask layer such as silicon nitride and an overlayer such as a TEOS deposited silicon oxide. Then photoresist is deposited and patterned to define an emitter window. Following nitride spacer formation and selective growth of a SiGe base, a silicon nitride is deposited and etched to form a second nitride spacer. Subsequently, a layer of doped polysilicon is deposited to form the emitter. Another hard mask layer may then be deposited over the polysilicon layer followed by a photoresist mask. At this point, the process involves systematic removal of the layers of material over the surface of the wafer other than the regions in which the bi-polar devices are formed, e.g., the CMOS regions.
One result of the above described deposition sequence is that the layers of deposited material create a surface that is not flat, i.e., because the surface may have various vertically extending features such as a CMOS gate stack. As subsequent layers are formed above the semiconductor wafer, they extend over these vertically oriented features and appear as sidewall layers along the sides of the devices. Quite often, these sidewalls, when measured perpendicularly to the wafer surface, are thicker than the layers along relatively flat surface regions of the wafer. As a result, when the layers are later removed, the process of removal for each layer may terminate before the vertically formed layer is completely removed. These remaining portions are typically referred to as stringers and have required additional processing for their removal thus contributing to a slower throughput in wafer processing.
Commonly, stringers that are left after formation of the bi-polar emitter and removal of the unused portions of the deposited layer may be formed of SiO2 (silicon dioxide) and SiOxNy (silicon oxi-nitride). In the past, removal of the SiO2 and SiOxNy stringers on or near the vertical sidewalls of a CMOS gate structure has been effected by overetching during hard mask removal to selectively remove the stringers. The overetching should avoid significant etching into the polysilicon layer that is used to form the bi-polar device emitter. The emitter is then defined using an etch chemistry which is selective with respect to SiO2. This limits the amount of silicon dioxide stringer removal. The combination of the hard mask etch and emitter etch, is self limiting with regard to the amount of stringer that can be removed. More particularly, the hard mask etch is limited by the process selectivity of silicon oxide to polysilicon while the poly emitter etch is typically selective toward silicon dioxide, only removing a limited amount of the stringer left over from the hard mask etch step. As a result, some bumps and/or stringers are left after etching, particularly in the tight spaces of the CMOS gate stack.